DV1465 / DV1505 / DV1511:

Compiler and Interpreter Technology

08:15 Wednesday 6th April, 2016

Between the IR and the target machine.

Table of Contents
DAGsTarget Machine
SSA
Further Interpreters

1. Roadmap type stuff

2. Motivation for using DAGs

x:= z**10 y:= z**10 + z*z // Avoid expensive recalculation
for(i=0; i<max; i++) buf[i+1] = buf[i] norm[i] = calc_norm(i+1, norm[i+1]) // Programmer convenience
y := x+1 x := x+1 z := x+1 // Oops, all that glitters is not gold.

3. Relation between block and DAG.

t0 <- i + 1 t1 <- t0 * 7 x <- t0 t2 <- t0 * 11 y <- t2

4. Building a DAG locally (value-numbering).

5. Building a DAG locally (value-numbering).

{ 2:0, x:1, (ADD 0 1):2, y:3, 3:4, (SUB 3 4):5, (ADD 2 5):6, (SUB 1 5):7, (MUL 6 7):8 }

6. Execution (partial order) on a DAG.

Topological sorts are a partial ordering of the DAG
There may be multiple topsorts of a DAG, each is a valid execution ordering, some may be faster than others

7. Data-flow representations of expressions

8. SSA removes state from the problem.

9. SSA requires phi-nodes to patch up control-flow.

10. SSA phi-nodes

11. Elimination of phi-nodes

12. Concrete Simulation

Starting point in the research literature
The Structure and Performance of Efficient Interpreters M. Anton Ertl, David Gregg

13. Current Research Trends

14. Current Research Trends

Break (15mins)





Intermission

15. The Target Machine

16. RISC vs CISC

17. X86_64

Size
64-bitraxrbxrcxrdxrsirdirbprspr8-r15
32-biteaxebxecxedxesiediebpespr8d-r15d
16-bitaxbxcxdxsidibpspr8w-r15w
8-bitalblcldlsildilbplsplr8b-r15b

18. Memory Hierarchy

  • The processor architecture defines:
    • The top-levels of the cache hierarchy.
    • Which operations get performed by programs.
    • How the programmer may affect control-flow.
  • Data movement between levels is expensive.
  • Data movement within the top level is free.
  • In order to calculate we need operands in level 0.
    • Most of our programs consist of expressions.
    • Parse-trees are mostly operator nodes.
    • Each one will be a calculation in the ALU.
  • Mostly generation is about getting them there.
    • "All programming is an exercise in caching." - Terje Mathisen
image/svg+xml L3: RAM L4+: OS L2: Cache L1: Cache L0: Registers ALU

19. Instruction overview

20. Data movement

21. Basic arithmetic

22. Bitwise Logic

23. Addressing Modes

24. Addressing modes

store: db 64; movl store, %eax; leal store, %eax;

25. Addressing modes

movl _y, %eax; movl (%eax), %eax; movl (%eax), %eax; movl _x, %ebx; movl %eax, (%ebx)

26. Addressing modes

movl _y, %eax; movl (%eax), %eax; movb 24(%eax), %al; movl _x, %ebx; movb %al, (%ebx) // x = *((char*)y+24)

27. Addressing modes

28. Summary